1. Field of the Invention
The present invention relates to a peak hold circuit and, more particularly, it relates to a peak hold circuit for sampling and holding the peak of a servo signal which is recorded on a hard disc or the like and used for tracking control, in driving the disc.
FIG. 1 is a circuit diagram showing this type of conventional peak hold circuit. Signals from servo signal input terminals 1a, 1b are applied to a full wave rectifier 2. Differential pair PNP transistors Q.sub.1 and Q.sub.2 are main elements of the full wave rectifier 2. The transistor Q.sub.1 has a base connected to the servo signal input terminal 1a through a capacitor C.sub.1 and also connected to a reference voltage source E.sub.1 through a resistor R.sub.1. The transistor Q.sub.1 has a collector connected to a power source v.sub.CC and an emitter connected to the emitter of the transistor Q.sub.2. A common junction of both of the emitters is connected to a constant current source I.sub.1. The transistor Q.sub.2 has a base connected to the servo signal input terminal 1b through a capacitor C.sub.2 and also connected to the reference voltage source E.sub.1 through a resistor R.sub.2. The transistor Q.sub.2 has a collector connected to the power source V.sub.CC.
NPN transistors Q.sub.3 and Q.sub.5 and a PNP transistor Q.sub.4 serve as an anti-stage buffer for a reference voltage. The transistor Q.sub.3 has a base connected to the reference voltage source E.sub.1 through a resistor R.sub.3, a collector connected to the power source v.sub.CC and an emitter connected to a constant current source I.sub.2. The transistor Q.sub.4 has a base connected to the emitter of the transistor Q.sub.3, a collector connected to the ground and an emitter connected to the power source V.sub.CC through a constant current source I.sub.3. The transistor Q.sub.5 has a base connected to the emitter of the transistor Q.sub.4, a collector connected to the power source V.sub.CC and an emitter connected to a post-stage buffer 3 for a reference voltage.
A PNP transistor Q.sub.6 and an NPN transistor Q.sub.7 serve as an anti-stage buffer for a servo signal. The transistor Q.sub.6 has a base connected to the common junction of the emitters of the transistors Q.sub.1 and Q.sub.2, an emitter connected to the power source V.sub.CC through a constant current source I.sub.4 and a collector connected to the ground. The transistor Q.sub.7 has a base connected to the emitter of the transistor Q.sub.6 and also connected to the ground through the series connection of a resistor R.sub.4 and a switch 4 for sampling and holding a servo signal, a collector connected to the power source V.sub.CC, and an emitter connected to the ground through a capacitor C.sub.3 for holding a servo signal and also connected to the input of a post-stage buffer 5 for a servo signal. The servo signal sampling and holding switch 4 turns ON/OFF in response to an input from a sampling pulse input terminal 8, and accordingly switches between the sampling mode and holding mode. Outputs from the post-stage reference voltage buffer 3 and post-stage servo signal buffer 5 are connected to minus and plus inputs of a subtractor 6, respectively. An output from the subtractor 6 is applied to a post-stage circuit 7.
Now, the operation of the conventional peak hold circuit will be described with reference to FIG. 2. Assume that a servo signal A, which is recorded in a servo region in a hard disc and has an amplitude of V.sub.s as shown in FIG. 2, is inputted to the servo signal input terminal 1a. A signal having a phase opposite to that of the servo signal A is inputted to the servo signal input terminal 1b. The full wave rectifier 2 rectifies the servo signal A and outputs a servo signal B having the peak value of (V.sub.ref +(1/2)V.sub.s) as shown in FIG. 2, where V.sub.ref is the reference voltage of the reference voltage source E.sub.1. The reference voltage V.sub.ref is applied to the minus input of the subtractor 6 through the transistors Q.sub.3, Q.sub.4 and Q.sub.5 and the post-stage reference voltage buffer 3.
In this situation, when a sampling pulse P inputted the sampling pulse input terminal 8 goes low as shown in FIG. 2, the servo signal sampling and holding switch 4 turns off. The transistor Q.sub.7 accordingly turns on, so that &he mode changes to the sampling mode. The servo signal C is applied to the holding capacitor C.sub.3 through the transistors Q.sub.6 and Q.sub.7. The servo signal holding capacitor C.sub.3 is charged to have the peak voltage (V.sub.ref +(1/2)Vs) of the servo signal C.
Meanwhile, when the sampling pulse P goes high, the servo signal sampling and holding switch 4 turns on. The transistor Q.sub.7 accordingly turns off, so that the mode changes to the holding mode. The charging voltage D of the holding capacitor C.sub.3 is applied to the plus input of the subtractor 6 through the post-stage servo signal buffer 5. The subtractor 6 subtracts an output voltage of the post-stage reference voltage buffer 3 from a output voltage of the post-stage servo signal buffer 5 and applies the difference between them to the post-stage circuit 7 which is a tracking control system. The post-stage circuit 7 conducts tracking control using the output voltage from the subtractor 6.
The conventional peak hold circuit structured as hereinbefore described has the following disadvantages.
A transistor Q.sub.10 is a main element of the post-stage servo signal buffer 5 as shown in FIG. 3. The transistor Q.sub.10 has a base connected to a common junction of the transistor Q.sub.7 and the servo signal holding capacitor C.sub.3, a collector connected to the power source V.sub.CC and an emitter connected to a constant current source I.sub.10 and also connected to the plus input of the subtractor 6. In the holding mode, the charging voltage of the servo signal holding capacitor C.sub.3 is discharged through the base of the transistor Q.sub.10, the emitter of the transistor Q.sub.10 and the constant current source I.sub.10 the ground, so that the charging voltage D of the holding capacitor C.sub.3 is reduced as time passes, as shown in FIG. 2. Consequently, the charging voltage D has a servo signal offset corresponding to an oblique line portion of FIG. 2.
Meanwhile, the reference voltage V.sub.ref is constant in any mode of the sampling mode and the holding mode as shown in FIG. 2. Accordingly, the output voltage I of the subtractor 6 includes an offset corresponding to the servo signal offset as shown with oblique lines in FIG. 2. As a result, with the output voltage I of the subtractor 6, tracking control can not be effected accurately.
Further, the servo region must be narrowed to increase information recorded in the hard disc. However, when the servo region is narrowed, a occurrence period of the servo signals A and C are shortened as shown in FIG. 4. This may cause a case in which the charging voltage D of the holding capacitor C.sub.3 does not reach the peak value (V.sub.ref +(1/2)V.sub.s) of the servo signal C as shown in FIG. 4. This, together with the above mentioned servo signal offset, results in that the output voltage I of the subtractor 6 has a large offset corresponding to an oblique line portion of in FIG. 4. As a result, tracking control can not be effected accurately. Moreover, in the case that the sampling period is short (i.e., the period for which the sampling pulse is low is short), also, disadvantages similar to the case in which the servo region is narrowed as previously mentioned are caused.